Loading…

The study of flat-band voltage shift using arsenic ion-implantation with High-k/Metal Inserted Poly Si gate stacks

The origin of flat band voltage shift phenomena using arsenic ion-implant in High-k/Metal Inserted Poly Si (HK/MIPS) gate stacks was investigated. Arsenic ion-implantations were carried out on HfSiO and HfSiON dielectric layers. Precise arsenic profile was obtained through front and backside SIMS an...

Full description

Saved in:
Bibliographic Details
Main Authors: BeomYong Kim, YunHyuck Ji, SeungMi Lee, BongSeok Jeon, KeeJeung Lee, Kwon Hong, SungKi Park
Format: Conference Proceeding
Language:English
Subjects:
Online Access:Request full text
Tags: Add Tag
No Tags, Be the first to tag this record!
cited_by
cites
container_end_page 82
container_issue
container_start_page 79
container_title
container_volume
creator BeomYong Kim
YunHyuck Ji
SeungMi Lee
BongSeok Jeon
KeeJeung Lee
Kwon Hong
SungKi Park
description The origin of flat band voltage shift phenomena using arsenic ion-implant in High-k/Metal Inserted Poly Si (HK/MIPS) gate stacks was investigated. Arsenic ion-implantations were carried out on HfSiO and HfSiON dielectric layers. Precise arsenic profile was obtained through front and backside SIMS analysis. From the electrical and physical analysis, we verified that the flat band voltage was shifted due to an arsenic dipole formation at high-k/metal interface. The negative shift of 480 mV was obtained with the optimized arsenic ion implant condition.
doi_str_mv 10.1109/ESSDERC.2011.6044230
format conference_proceeding
fullrecord <record><control><sourceid>ieee_6IE</sourceid><recordid>TN_cdi_ieee_primary_6044230</recordid><sourceformat>XML</sourceformat><sourcesystem>PC</sourcesystem><ieee_id>6044230</ieee_id><sourcerecordid>6044230</sourcerecordid><originalsourceid>FETCH-LOGICAL-i90t-4efe99e84ffb196bb1d5cc3e8ffa665dcbc2289e44ff83ff3d0ca2a49f097e1d3</originalsourceid><addsrcrecordid>eNpVUM1OwzAYCwIkJtgTwCEvkC1p0_wc0Rhs0hCI7T6lyZc2rGunJgPt7SliF3yxLFu2ZIQeGJ0wRvV0vl4_zT9mk4wyNhGU8yynF2ispWK8kJJKquTlPy3pFRoxnVOilBQ3aBzjJx0ghC6UGqF-UwOO6ehOuPPYNyaR0rQOf3VNMtVg1cEnfIyhrbDpI7TB4tC1JOwPjWmTSYPA3yHVeBGqmuymr5BMg5dthD6Bw-9dc8LrgCuTfneM3cU7dO1NE2F85lu0eZ5vZguyentZzh5XJGiaCAcPWoPi3pdMi7JkrrA2B-W9EaJwtrRZpjTwIaBy73NHrckM155qCczlt-j-rzYAwPbQh73pT9vzafkP70BhIw</addsrcrecordid><sourcetype>Publisher</sourcetype><iscdi>true</iscdi><recordtype>conference_proceeding</recordtype></control><display><type>conference_proceeding</type><title>The study of flat-band voltage shift using arsenic ion-implantation with High-k/Metal Inserted Poly Si gate stacks</title><source>IEEE Electronic Library (IEL) Conference Proceedings</source><creator>BeomYong Kim ; YunHyuck Ji ; SeungMi Lee ; BongSeok Jeon ; KeeJeung Lee ; Kwon Hong ; SungKi Park</creator><creatorcontrib>BeomYong Kim ; YunHyuck Ji ; SeungMi Lee ; BongSeok Jeon ; KeeJeung Lee ; Kwon Hong ; SungKi Park</creatorcontrib><description>The origin of flat band voltage shift phenomena using arsenic ion-implant in High-k/Metal Inserted Poly Si (HK/MIPS) gate stacks was investigated. Arsenic ion-implantations were carried out on HfSiO and HfSiON dielectric layers. Precise arsenic profile was obtained through front and backside SIMS analysis. From the electrical and physical analysis, we verified that the flat band voltage was shifted due to an arsenic dipole formation at high-k/metal interface. The negative shift of 480 mV was obtained with the optimized arsenic ion implant condition.</description><identifier>ISSN: 1930-8876</identifier><identifier>ISBN: 9781457707070</identifier><identifier>ISBN: 1457707071</identifier><identifier>EISBN: 9781457707087</identifier><identifier>EISBN: 145770708X</identifier><identifier>EISBN: 1457707063</identifier><identifier>EISBN: 9781457707063</identifier><identifier>DOI: 10.1109/ESSDERC.2011.6044230</identifier><language>eng</language><publisher>IEEE</publisher><subject>Capacitance-voltage characteristics ; Implants ; Logic gates ; MOS capacitors ; Nitrogen ; Silicon ; Tin</subject><ispartof>2011 Proceedings of the European Solid-State Device Research Conference (ESSDERC), 2011, p.79-82</ispartof><woscitedreferencessubscribed>false</woscitedreferencessubscribed></display><links><openurl>$$Topenurl_article</openurl><openurlfulltext>$$Topenurlfull_article</openurlfulltext><thumbnail>$$Tsyndetics_thumb_exl</thumbnail><linktohtml>$$Uhttps://ieeexplore.ieee.org/document/6044230$$EHTML$$P50$$Gieee$$H</linktohtml><link.rule.ids>309,310,776,780,785,786,2051,27904,54534,54899,54911</link.rule.ids><linktorsrc>$$Uhttps://ieeexplore.ieee.org/document/6044230$$EView_record_in_IEEE$$FView_record_in_$$GIEEE</linktorsrc></links><search><creatorcontrib>BeomYong Kim</creatorcontrib><creatorcontrib>YunHyuck Ji</creatorcontrib><creatorcontrib>SeungMi Lee</creatorcontrib><creatorcontrib>BongSeok Jeon</creatorcontrib><creatorcontrib>KeeJeung Lee</creatorcontrib><creatorcontrib>Kwon Hong</creatorcontrib><creatorcontrib>SungKi Park</creatorcontrib><title>The study of flat-band voltage shift using arsenic ion-implantation with High-k/Metal Inserted Poly Si gate stacks</title><title>2011 Proceedings of the European Solid-State Device Research Conference (ESSDERC)</title><addtitle>ESSDERC</addtitle><description>The origin of flat band voltage shift phenomena using arsenic ion-implant in High-k/Metal Inserted Poly Si (HK/MIPS) gate stacks was investigated. Arsenic ion-implantations were carried out on HfSiO and HfSiON dielectric layers. Precise arsenic profile was obtained through front and backside SIMS analysis. From the electrical and physical analysis, we verified that the flat band voltage was shifted due to an arsenic dipole formation at high-k/metal interface. The negative shift of 480 mV was obtained with the optimized arsenic ion implant condition.</description><subject>Capacitance-voltage characteristics</subject><subject>Implants</subject><subject>Logic gates</subject><subject>MOS capacitors</subject><subject>Nitrogen</subject><subject>Silicon</subject><subject>Tin</subject><issn>1930-8876</issn><isbn>9781457707070</isbn><isbn>1457707071</isbn><isbn>9781457707087</isbn><isbn>145770708X</isbn><isbn>1457707063</isbn><isbn>9781457707063</isbn><fulltext>true</fulltext><rsrctype>conference_proceeding</rsrctype><creationdate>2011</creationdate><recordtype>conference_proceeding</recordtype><sourceid>6IE</sourceid><recordid>eNpVUM1OwzAYCwIkJtgTwCEvkC1p0_wc0Rhs0hCI7T6lyZc2rGunJgPt7SliF3yxLFu2ZIQeGJ0wRvV0vl4_zT9mk4wyNhGU8yynF2ispWK8kJJKquTlPy3pFRoxnVOilBQ3aBzjJx0ghC6UGqF-UwOO6ehOuPPYNyaR0rQOf3VNMtVg1cEnfIyhrbDpI7TB4tC1JOwPjWmTSYPA3yHVeBGqmuymr5BMg5dthD6Bw-9dc8LrgCuTfneM3cU7dO1NE2F85lu0eZ5vZguyentZzh5XJGiaCAcPWoPi3pdMi7JkrrA2B-W9EaJwtrRZpjTwIaBy73NHrckM155qCczlt-j-rzYAwPbQh73pT9vzafkP70BhIw</recordid><startdate>201109</startdate><enddate>201109</enddate><creator>BeomYong Kim</creator><creator>YunHyuck Ji</creator><creator>SeungMi Lee</creator><creator>BongSeok Jeon</creator><creator>KeeJeung Lee</creator><creator>Kwon Hong</creator><creator>SungKi Park</creator><general>IEEE</general><scope>6IE</scope><scope>6IL</scope><scope>CBEJK</scope><scope>RIE</scope><scope>RIL</scope></search><sort><creationdate>201109</creationdate><title>The study of flat-band voltage shift using arsenic ion-implantation with High-k/Metal Inserted Poly Si gate stacks</title><author>BeomYong Kim ; YunHyuck Ji ; SeungMi Lee ; BongSeok Jeon ; KeeJeung Lee ; Kwon Hong ; SungKi Park</author></sort><facets><frbrtype>5</frbrtype><frbrgroupid>cdi_FETCH-LOGICAL-i90t-4efe99e84ffb196bb1d5cc3e8ffa665dcbc2289e44ff83ff3d0ca2a49f097e1d3</frbrgroupid><rsrctype>conference_proceedings</rsrctype><prefilter>conference_proceedings</prefilter><language>eng</language><creationdate>2011</creationdate><topic>Capacitance-voltage characteristics</topic><topic>Implants</topic><topic>Logic gates</topic><topic>MOS capacitors</topic><topic>Nitrogen</topic><topic>Silicon</topic><topic>Tin</topic><toplevel>online_resources</toplevel><creatorcontrib>BeomYong Kim</creatorcontrib><creatorcontrib>YunHyuck Ji</creatorcontrib><creatorcontrib>SeungMi Lee</creatorcontrib><creatorcontrib>BongSeok Jeon</creatorcontrib><creatorcontrib>KeeJeung Lee</creatorcontrib><creatorcontrib>Kwon Hong</creatorcontrib><creatorcontrib>SungKi Park</creatorcontrib><collection>IEEE Electronic Library (IEL) Conference Proceedings</collection><collection>IEEE Proceedings Order Plan All Online (POP All Online) 1998-present by volume</collection><collection>IEEE Xplore All Conference Proceedings</collection><collection>IEEE Xplore (IEEE/IET Electronic Library - IEL)</collection><collection>IEEE Proceedings Order Plans (POP All) 1998-Present</collection></facets><delivery><delcategory>Remote Search Resource</delcategory><fulltext>fulltext_linktorsrc</fulltext></delivery><addata><au>BeomYong Kim</au><au>YunHyuck Ji</au><au>SeungMi Lee</au><au>BongSeok Jeon</au><au>KeeJeung Lee</au><au>Kwon Hong</au><au>SungKi Park</au><format>book</format><genre>proceeding</genre><ristype>CONF</ristype><atitle>The study of flat-band voltage shift using arsenic ion-implantation with High-k/Metal Inserted Poly Si gate stacks</atitle><btitle>2011 Proceedings of the European Solid-State Device Research Conference (ESSDERC)</btitle><stitle>ESSDERC</stitle><date>2011-09</date><risdate>2011</risdate><spage>79</spage><epage>82</epage><pages>79-82</pages><issn>1930-8876</issn><isbn>9781457707070</isbn><isbn>1457707071</isbn><eisbn>9781457707087</eisbn><eisbn>145770708X</eisbn><eisbn>1457707063</eisbn><eisbn>9781457707063</eisbn><abstract>The origin of flat band voltage shift phenomena using arsenic ion-implant in High-k/Metal Inserted Poly Si (HK/MIPS) gate stacks was investigated. Arsenic ion-implantations were carried out on HfSiO and HfSiON dielectric layers. Precise arsenic profile was obtained through front and backside SIMS analysis. From the electrical and physical analysis, we verified that the flat band voltage was shifted due to an arsenic dipole formation at high-k/metal interface. The negative shift of 480 mV was obtained with the optimized arsenic ion implant condition.</abstract><pub>IEEE</pub><doi>10.1109/ESSDERC.2011.6044230</doi><tpages>4</tpages></addata></record>
fulltext fulltext_linktorsrc
identifier ISSN: 1930-8876
ispartof 2011 Proceedings of the European Solid-State Device Research Conference (ESSDERC), 2011, p.79-82
issn 1930-8876
language eng
recordid cdi_ieee_primary_6044230
source IEEE Electronic Library (IEL) Conference Proceedings
subjects Capacitance-voltage characteristics
Implants
Logic gates
MOS capacitors
Nitrogen
Silicon
Tin
title The study of flat-band voltage shift using arsenic ion-implantation with High-k/Metal Inserted Poly Si gate stacks
url http://sfxeu10.hosted.exlibrisgroup.com/loughborough?ctx_ver=Z39.88-2004&ctx_enc=info:ofi/enc:UTF-8&ctx_tim=2025-01-23T10%3A48%3A44IST&url_ver=Z39.88-2004&url_ctx_fmt=infofi/fmt:kev:mtx:ctx&rfr_id=info:sid/primo.exlibrisgroup.com:primo3-Article-ieee_6IE&rft_val_fmt=info:ofi/fmt:kev:mtx:book&rft.genre=proceeding&rft.atitle=The%20study%20of%20flat-band%20voltage%20shift%20using%20arsenic%20ion-implantation%20with%20High-k/Metal%20Inserted%20Poly%20Si%20gate%20stacks&rft.btitle=2011%20Proceedings%20of%20the%20European%20Solid-State%20Device%20Research%20Conference%20(ESSDERC)&rft.au=BeomYong%20Kim&rft.date=2011-09&rft.spage=79&rft.epage=82&rft.pages=79-82&rft.issn=1930-8876&rft.isbn=9781457707070&rft.isbn_list=1457707071&rft_id=info:doi/10.1109/ESSDERC.2011.6044230&rft.eisbn=9781457707087&rft.eisbn_list=145770708X&rft.eisbn_list=1457707063&rft.eisbn_list=9781457707063&rft_dat=%3Cieee_6IE%3E6044230%3C/ieee_6IE%3E%3Cgrp_id%3Ecdi_FETCH-LOGICAL-i90t-4efe99e84ffb196bb1d5cc3e8ffa665dcbc2289e44ff83ff3d0ca2a49f097e1d3%3C/grp_id%3E%3Coa%3E%3C/oa%3E%3Curl%3E%3C/url%3E&rft_id=info:oai/&rft_id=info:pmid/&rft_ieee_id=6044230&rfr_iscdi=true