High Throughput Data Mapping for Coarse-Grained Reconfigurable Architectures

Coarse-grained reconfigurable arrays (CGRAs) are a very promising platform, providing both up to 10-100 MOps/mW of power efficiency and software programmability. However, this promise of CGRAs critically hinges on the effectiveness of application mapping onto CGRA platforms. While previous solutions...

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Bibliographic Details
Published in:IEEE transactions on computer-aided design of integrated circuits and systems 2011-11, Vol.30 (11), p.1599-1609
Main Authors: Yongjoo Kim, Jongeun Lee, Shrivastava, A., Yoon, J. W., Doosan Cho, Yunheung Paek
Format: Article
Language:English
Subjects:
Array mapping
Arrays
bank conflict
coarse-grained reconfigurable architecture
compilation
Computer programs
Mapping
Materials handling
Mathematical models
Memory architecture
Memory management
multi-bank memory
Network architecture
Platforms
Reduction
Software
Studies
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Summary:Coarse-grained reconfigurable arrays (CGRAs) are a very promising platform, providing both up to 10-100 MOps/mW of power efficiency and software programmability. However, this promise of CGRAs critically hinges on the effectiveness of application mapping onto CGRA platforms. While previous solutions have greatly improved the computation speed, they have largely ignored the impact of the local memory architecture on the achievable power and performance. This paper motivates the need for memory-aware application mapping for CGRAs, and proposes an effective solution for application mapping that considers the effects of various memory architecture parameters including the number of banks, local memory size, and the communication bandwidth between the local memory and the external main memory. Further we propose efficient methods to handle dependent data on a double-buffering local memory, which is necessary for recurrent loops. Our proposed solution achieves 59% reduction in the energy-delay product, which factors into about 47% and 22% reduction in the energy consumption and runtime, respectively, as compared to memory-unaware mapping for realistic local memory architectures. We also show that our scheme scales across a range of applications and memory parameters, and the runtime overhead of handling recurrent loops by our proposed methods can be less than 1%.
ISSN:0278-0070
1937-4151
DOI:10.1109/TCAD.2011.2161217