A 19 mW/lane Serdes transceiver for SFI-5.1 application

A low-power, small-area transceiver PHY that supports SFI-5.1 is fabricated in standard 40 nm CMOS, supporting rates up to 50 Gb/s. The combined active core area of the receiver (RX) and transmitter (TX) occupies only 0.08 mm 2 per lane. The RX can handle 0.65 UI (RJ + DJ) plus 0.49 UI additional si...

Full description

Saved in:
Bibliographic Details
Main Authors: Fallahi, S., Delong Cui, Deyi Pi, Zhu, R., Unruh, G., Lugthart, M., Momtaz, A.
Format: Conference Proceeding
Language:English
Subjects:
Clocks
CMOS integrated circuits
Finite impulse response filter
Jitter
Noise
Phase locked loops
Receivers
SerDes
SFI-5.1
transceivers and ADPLL
Online Access:Request full text
Tags: Add Tag
No Tags, Be the first to tag this record!
Description
Summary:A low-power, small-area transceiver PHY that supports SFI-5.1 is fabricated in standard 40 nm CMOS, supporting rates up to 50 Gb/s. The combined active core area of the receiver (RX) and transmitter (TX) occupies only 0.08 mm 2 per lane. The RX can handle 0.65 UI (RJ + DJ) plus 0.49 UI additional sinusoidal input jitter, and the TX has only 5.4 ps of ISI. Sixteen lanes plus deskew and clock source channels consume 19 mW of power at 3.125 Gb/s per lane.
ISSN:0886-5930
2152-3630
DOI:10.1109/CICC.2011.6055361