Flip-chip and chip-scale I/O density requirements and printed wiring board capabilities

• Main Authors: Guinn, K.V., Frye, R.C.
• Format: Conference Proceeding
• Language: English
• Subjects: Ceramics; Chip scale packaging; CMOS technology; Costs; Electronics packaging; Integrated circuit packaging; Joining processes; Microprocessors; Routing; Wiring
• ISSN: 0569-5503; 2377-5726
• DOI: 10.1109/ECTC.1997.606240

Flip-chip and chip-scale packaging can increase the packaging density for integrated circuits on printed wiring boards and multichip modules. However, these approaches can result in I/O configurations that exceed the routing capabilities of the underlying board. We have examined the I/O density requirements of a wide variety of integrated circuit types. Simple linear ICs and gates are at one extreme, with few I/O and small area, and high-end microprocessors are at the other, with many I/O and large area. We analyze a representative routing escape strategy for area-array I/O, and use this analysis to determine the packaging limits of several different board technologies. Comparing these limits to the I/O configurations of various ICs in flip-chip and chip scale packages, we identify some classes of circuits (e.g., memory) that are more readily suited to conventional boards, and others (e.g., high end microprocessors) that will require very aggressive board technologies. We show that a successful overall packaging strategy will balance that need for high density chip packaging and smaller boards against the demands that these packages will make on the routing capabilities and cost per unit area of printed wiring boards.