A reusable embedded DRAM macrocell

A charged based analysis is used to compare three DRAM cells embedded in a 0.25 /spl mu/m ASIC environment. Critical charge, bit-line response, and sense amplifier sensitivity are calculated. Wafer probe measurements are shown that demonstrate milli-second hold times and explanations presented in su...

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Bibliographic Details
Main Authors: Diodato, P.W., Clemens, J.T., Troutman, W.W., Lindenberger, W.S.
Format: Conference Proceeding
Language:English
Subjects:
Application specific integrated circuits
Capacitors
Design methodology
Fabrication
Macrocell networks
Parasitic capacitance
Probes
Random access memory
Robustness
Voltage
Online Access:Request full text
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Summary:A charged based analysis is used to compare three DRAM cells embedded in a 0.25 /spl mu/m ASIC environment. Critical charge, bit-line response, and sense amplifier sensitivity are calculated. Wafer probe measurements are shown that demonstrate milli-second hold times and explanations presented in support of using multi-transistor DRAM cells for the vast majority of high performance embedded ASIC applications.
DOI:10.1109/CICC.1997.606642