Low power CORDIC implementation using redundant number representation

In this paper a methodology for reducing the power consumption of shift-and-add operations in general and especially of CORDIC stages is presented. The proposed method uses the fact of simultaneous carry generation in redundant carry-save and signed digit structures to predict the minimum necessary...

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Bibliographic Details
Main Authors: Schimpfle, C.V., Simon, S., Nossek, J.A.
Format: Conference Proceeding
Language:English
Subjects:
Adders
Capacitance
Circuit synthesis
Design automation
Design methodology
Design optimization
Energy consumption
Hardware
High level synthesis
Power dissipation
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Summary:In this paper a methodology for reducing the power consumption of shift-and-add operations in general and especially of CORDIC stages is presented. The proposed method uses the fact of simultaneous carry generation in redundant carry-save and signed digit structures to predict the minimum necessary hardware effort for shift-and-add operations. As a carry once generated in a certain bit position cannot "ripple" through the adder if using redundant number representation, hardware parts can be switched on or off depending on the shift constant. Simulations have shown, that shift dependent hardware utilization of parallel implementations leads to monotonically decreasing power consumption for increasing shift constants. A CORDIC processor element for 16 digit SDNR has been implemented as a layout and simulated with PowerMill in terms of power consumption.
ISSN:2160-0511
2160-052X
DOI:10.1109/ASAP.1997.606822