32-bit reconfigurable logic-BIST design using Verilog for ASIC chips

The BIST technique for logic circuits improves access to internal signals from primary input/outputs. This paper presents programmable logic BIST architecture for testing ASIC chips. The scheme is based on STUMPS [6] (Self Test Using MISR [4, 6] and Parallel Shift register) architecture which uses a...

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Bibliographic Details
Main Authors: Bhakthavatchalu, R., Deepthy, G. R., Mallia, S. S., HariKrishnan, R., Krishnan, Arun, Sruthi, B.
Format: Conference Proceeding
Language:English
Subjects:
ASIC testing
at speed testing
ATPG
Built-in self-test
Circuit faults
DFT
Integrated circuits
Logic BIST
MISR
Multi voltage Design
Polynomials
Power Analysis
PRPG
Scan test
Shift registers
STUMPS
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Summary:The BIST technique for logic circuits improves access to internal signals from primary input/outputs. This paper presents programmable logic BIST architecture for testing ASIC chips. The scheme is based on STUMPS [6] (Self Test Using MISR [4, 6] and Parallel Shift register) architecture which uses an on-chip circuitry to generate the test patterns and analyze the responses with no or little help from an ATE. External operations are required only to initialize the Built-in tests and to check the test results. The system is synthesized in Xilinx ISE 10.1 to get the frequency of operation and in Design Compiler for timing Analysis. Multi Voltage design for power reduction is successfully implemented.
DOI:10.1109/RAICS.2011.6069340