Impact and optimization of lithography-aware regular layout in digital circuit design

Regular fabrics are expected to mitigate manufacturing process variations, increasing fabrication yield in deep sub-micron CMOS technologies. This paper presents an extensive analysis of aspects involved in the optimization of regular fabric (based) designs. The choice of the most efficient regular...

Full description

Saved in:
Bibliographic Details
Main Authors: Dal Bem, V., Butzen, P., Marranghello, F. S., Reis, A. I., Ribas, R. P.
Format: Conference Proceeding
Language:English
Subjects:
Benchmark testing
CMOS digital circuits
Fabrics
Layout
layout pattern optimization
Libraries
lithography-aware design
Logic gates
Optimization
regular fabric
standard cells
structured ASIC
Transistor regular layout
Transistors
Online Access:Request full text
Tags: Add Tag
No Tags, Be the first to tag this record!
Description
Summary:Regular fabrics are expected to mitigate manufacturing process variations, increasing fabrication yield in deep sub-micron CMOS technologies. This paper presents an extensive analysis of aspects involved in the optimization of regular fabric (based) designs. The choice of the most efficient regular fabric design strategy depends on the area overhead and circuit performance degradation, which may vary according the fabric pattern optimization possibilities. Yield improvements have to be traded-off against area and performance losses due to regular design rules. This paper evaluates the losses introduced by using regular fabrics. Several benchmark circuits have been mapped over different regular layout templates through specific cell libraries built for this purpose. Results have demonstrated that the design impact is quite manageable by choosing appropriately the fabric pattern or template.
ISSN:1063-6404
2576-6996
DOI:10.1109/ICCD.2011.6081409