The verification of network processor Fast Bus Interface using SystemVerilog

According to the background of network processor XDNP, this article describes a design of Fast Bus Interface(FBI) verification platform based on VMM architecture. All of the components and codes in the verification platform are achieved by SystemVerilog and assertions are also used in the process of...

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Bibliographic Details
Main Authors: Ma Pei-Jun, Ma Wen-Bo, Li Kang, Shi Jiang-Yi, Jiang Yong
Format: Conference Proceeding
Language:English
Subjects:
assertion
Educational institutions
Fast Bus Interface
FBI
Generators
Microelectronics
Monitoring
Presses
SDRAM
System-on-a-chip
SystemVerilog
verification
VMM
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Summary:According to the background of network processor XDNP, this article describes a design of Fast Bus Interface(FBI) verification platform based on VMM architecture. All of the components and codes in the verification platform are achieved by SystemVerilog and assertions are also used in the process of verification. Through resonable usage of SVA it bacomes much easier to check out errors occuring in the executive process of FBI quickly and exactly. And then, the valuable functional verification results are obtained.
DOI:10.1109/EDSSC.2011.6117669