Extending HyperTransport™ technology to 8.0 Gb/s in 32-nm SOI-CMOS processors

We present an 8.0-Gb/s HyperTransport™ technology I/O built in a 32-nm SOI-CMOS processor for high-performance servers. Based on a 45-nm design that caps at 6.4 Gb/s, the 32-nm transceiver achieves up to 8.0 Gb/s over long-reach board channels. Key enhancements include a high-bandwidth (>;200 MHz...

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Bibliographic Details
Main Authors: Doyle, B. A., Loke, A. L. S., Maheshwari, S. K., Wang, C. L., Fischette, D. M., Cooper, J. G., Aggarwal, S. K., Wee, T. T., Lackey, C. O., Kedarnath, H. S., Oshima, M. M., Talbot, G. R., Fang, E. S.
Format: Conference Proceeding
Language:English
Subjects:
Bandwidth
Bit error rate
Clocks
Frequency modulation
Jitter
Phase locked loops
Program processors
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Summary:We present an 8.0-Gb/s HyperTransport™ technology I/O built in a 32-nm SOI-CMOS processor for high-performance servers. Based on a 45-nm design that caps at 6.4 Gb/s, the 32-nm transceiver achieves up to 8.0 Gb/s over long-reach board channels. Key enhancements include a high-bandwidth (>;200 MHz) PLL to attenuate high-frequency jitter in the received forwarded clock and redesigned power-hungry circuits to operate at 8.0 Gb/s within the existing 45-nm package thermal limit.
DOI:10.1109/ASSCC.2011.6123620