Design and Implementation of a Simplified Turbo Decoder for 3GPP2

In this paper a VLSI architecture for a configurable turbo decoder, compliant with the 3GPP2 standard is presented. A simple modification of the conventional iterative structure of a turbo decoder is presented, where one of the constituent interleavers can be eliminated, allowing an important reduct...

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Bibliographic Details
Main Authors: Yllescas-Calderon, L. C., Espino-Orozco, A. J., Parra-Michel, R., Gonzalez-Perez, Luis F.
Format: Conference Proceeding
Language:English
Subjects:
3GPP2
channel coding
Computer architecture
Decoding
finite precision analysis
Hardware
Interleaver
Iterative decoding
Measurement
sliding window
Systematics
Turbo codes
VLSI architectures
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Description
Summary:In this paper a VLSI architecture for a configurable turbo decoder, compliant with the 3GPP2 standard is presented. A simple modification of the conventional iterative structure of a turbo decoder is presented, where one of the constituent interleavers can be eliminated, allowing an important reduction in the overall complexity of the turbo decoder with no performance degradations. Performance analysis is highlighted vis `a vis a fixed point reference model. In addition, results of the overall architecture with the sliding window approach and implemented on an Alter a device is shown.
ISSN:2325-6532
2640-0472
DOI:10.1109/ReConFig.2011.25