A recovery mechanism for SET protection using standard-cells

The traditional way for protecting a digital circuit against Single Event Transients (SET) implies the triplication and voting of the combinational logic in the circuit. This approach uses a high area overhead. Other approaches imply the design of specific SET hardened cells, but they are rarely ava...

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Bibliographic Details
Main Authors: Garbayo, J. M. A., Valderas, M. G., Garcia, M. P., Ongil, C. L., Entrena, L.
Format: Conference Proceeding
Language:English
Subjects:
Circuit faults
Clocks
Detectors
Fault Tolerance
Flip-flops
Image edge detection
Logic gates
Redundancy
SET
Soft Error
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Summary:The traditional way for protecting a digital circuit against Single Event Transients (SET) implies the triplication and voting of the combinational logic in the circuit. This approach uses a high area overhead. Other approaches imply the design of specific SET hardened cells, but they are rarely available. In this paper a technique for detecting and correcting radiation-induced soft errors in combinational logic is presented. This technique offers a good protection against SET effects, with a reasonable area overhead compared to those of TMR approaches, and with little impact in the circuit performance. In addition, the proposed method uses standard cells from ASIC libraries and can be easily integrated in common ASIC design flows and tools. Results show that with this proposal, SET effects can be reduced between 90% to 100%, depending on the SET pulse width.
ISSN:0379-6566
DOI:10.1109/RADECS.2011.6131297