TSV fault-tolerant mechanisms with application to 3D clock networks

Three-dimensional integrated circuit (3D IC) has become an emerging technology in view of its advantages in packing density and flexibility in heterogeneous integration. Through Silicon Via (TSV) formation is one of the key enabling technologies for 3D ICs. While TSVs provide vertical connections be...

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Bibliographic Details
Main Authors: Chiao-Ling Lung, Jui-Hung Chien, Yiyu Shi, Shih-Chieh Chang
Format: Conference Proceeding
Language:English
Subjects:
3D IC
Clock Network
Clock Tree Synthesis
Double TSV
Fault-tolerant
Redundant Tree
Shared Spare TSV
Through-Silicon Via
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Summary:Three-dimensional integrated circuit (3D IC) has become an emerging technology in view of its advantages in packing density and flexibility in heterogeneous integration. Through Silicon Via (TSV) formation is one of the key enabling technologies for 3D ICs. While TSVs provide vertical connections between different dies for higher performance, they suffer from random open defects and thermo-mechanical stress. The potential yield loss can significantly increase the mass production cost, which in turn affects the profitability of 3D ICs. To address the TSV reliability issues, double TSV, shared spare TSV and TSV fault tolerant unit (TFU) techniques have been developed. In this paper, we briefly review them and use 3D clock networks as a vehicle to compare their effectiveness and overhead.
DOI:10.1109/ISOCC.2011.6138663