A scalable multi-ASIP architecture for standard compliant trellis decoding

Multi standard wireless modems are already becoming more and more important in industry. The recent move for LTE will aggravate this issue. We present a heterogeneous channel decoding architecture, which contains a scalable multi-ASIP cluster to support multiple legacy standards, while being able to...

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Bibliographic Details
Main Authors: Brehm, C., Ilnseher, T., Wehn, N.
Format: Conference Proceeding
Language:English
Subjects:
ASIP
Core
LTE
MPSoC
Multi Core
Processor
SDR
standard-driven
Turbo Code
UMTS
Viterbi
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Summary:Multi standard wireless modems are already becoming more and more important in industry. The recent move for LTE will aggravate this issue. We present a heterogeneous channel decoding architecture, which contains a scalable multi-ASIP cluster to support multiple legacy standards, while being able to offload the bulk of LTE decoding to an heavily optimized decoder to achieve a very good power efficiency. The energy efficiency in a 65 nm process node is 0.3 nj/bit/iter for LTE turbo code decoding and 0.69 nj/bit/iter for legacy standards.
DOI:10.1109/ISOCC.2011.6138782