Test clock domain optimization for peak power supply noise reduction during scan

This paper presents a design for testability (DfT) technique to reduce the peak power supply noise (PPSN) during scan chain shifting. The proposed partition technique reduces the maximum flip-flop density that belongs to the same test clock. The experimental data on large benchmark circuits show tha...

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Bibliographic Details
Main Authors: Jen-Yang Wen, Yu-Chuan Huang, Min-Hong Tsai, Kuan-Yu Liao, Li, J. C-M, Ming-Tung Chang, Min-Hsiu Tsai, Chih-Mou Tseng, Hung-Chun Li
Format: Conference Proceeding
Language:English
Subjects:
Automatic test pattern generation
Benchmark testing
Clocks
Flip-flops
Logic gates
Optimization
Power supplies
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Summary:This paper presents a design for testability (DfT) technique to reduce the peak power supply noise (PPSN) during scan chain shifting. The proposed partition technique reduces the maximum flip-flop density that belongs to the same test clock. The experimental data on large benchmark circuits show that IR drop are reduced by 38.7% on the average compared with the circuit before optimization. Our proposed technique quickly optimizes a half million gate design within 14 minutes while the commercial IR drop simulation tool took over 3 hours.
ISSN:1089-3539
2378-2250
DOI:10.1109/TEST.2011.6139163