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A new improved current mode logic style with feedback for wireless communication
In this paper, a new logic style named as MOS current mode logic with feedback (MCML-FB) is proposed as an alternative to conventional MOS current mode logic (MCML) for implementing digital circuits in wireless communication systems. The proposed circuit style combines the advantages of conventional...
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creator | Sridhar, R. Gupta, K. Pandey, N. Gupta, M. |
description | In this paper, a new logic style named as MOS current mode logic with feedback (MCML-FB) is proposed as an alternative to conventional MOS current mode logic (MCML) for implementing digital circuits in wireless communication systems. The proposed circuit style combines the advantages of conventional MCML and positive feedback to improve the performance of wireless systems. The use of feedback enhances the switching speed of the circuit without increasing its power consumption and also reduces the transistors count. Different MCML-FB based circuits such as XOR, carry and 4-bit ripple carry adder are proposed and simulated in PSPICE using 0.18μm CMOS technology parameters. The simulation results shows that the proposed circuits are faster and have less transistors in comparison to conventional MCML circuits. Monte Carlo simulations has also been conducted for both the logic styles to study the effect of process variations and the results shows that the proposed circuits are more prone to variations than the conventional one. |
doi_str_mv | 10.1109/INDCON.2011.6139503 |
format | conference_proceeding |
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The proposed circuit style combines the advantages of conventional MCML and positive feedback to improve the performance of wireless systems. The use of feedback enhances the switching speed of the circuit without increasing its power consumption and also reduces the transistors count. Different MCML-FB based circuits such as XOR, carry and 4-bit ripple carry adder are proposed and simulated in PSPICE using 0.18μm CMOS technology parameters. The simulation results shows that the proposed circuits are faster and have less transistors in comparison to conventional MCML circuits. Monte Carlo simulations has also been conducted for both the logic styles to study the effect of process variations and the results shows that the proposed circuits are more prone to variations than the conventional one.</description><identifier>ISSN: 2325-940X</identifier><identifier>ISBN: 9781457711107</identifier><identifier>ISBN: 1457711109</identifier><identifier>EISBN: 9781457711084</identifier><identifier>EISBN: 1457711087</identifier><identifier>EISBN: 1457711095</identifier><identifier>EISBN: 9781457711091</identifier><identifier>DOI: 10.1109/INDCON.2011.6139503</identifier><language>eng</language><publisher>IEEE</publisher><subject>Adders ; Capacitance ; CMOS integrated circuits ; high speed ; Logic gates ; MOS current mode logic ; Noise ; RCA ; Transistors ; Wireless communication</subject><ispartof>2011 Annual IEEE India Conference, 2011, p.1-4</ispartof><woscitedreferencessubscribed>false</woscitedreferencessubscribed></display><links><openurl>$$Topenurl_article</openurl><openurlfulltext>$$Topenurlfull_article</openurlfulltext><thumbnail>$$Tsyndetics_thumb_exl</thumbnail><linktohtml>$$Uhttps://ieeexplore.ieee.org/document/6139503$$EHTML$$P50$$Gieee$$H</linktohtml><link.rule.ids>309,310,776,780,785,786,2052,27902,54530,54895,54907</link.rule.ids><linktorsrc>$$Uhttps://ieeexplore.ieee.org/document/6139503$$EView_record_in_IEEE$$FView_record_in_$$GIEEE</linktorsrc></links><search><creatorcontrib>Sridhar, R.</creatorcontrib><creatorcontrib>Gupta, K.</creatorcontrib><creatorcontrib>Pandey, N.</creatorcontrib><creatorcontrib>Gupta, M.</creatorcontrib><title>A new improved current mode logic style with feedback for wireless communication</title><title>2011 Annual IEEE India Conference</title><addtitle>INDCON</addtitle><description>In this paper, a new logic style named as MOS current mode logic with feedback (MCML-FB) is proposed as an alternative to conventional MOS current mode logic (MCML) for implementing digital circuits in wireless communication systems. The proposed circuit style combines the advantages of conventional MCML and positive feedback to improve the performance of wireless systems. The use of feedback enhances the switching speed of the circuit without increasing its power consumption and also reduces the transistors count. Different MCML-FB based circuits such as XOR, carry and 4-bit ripple carry adder are proposed and simulated in PSPICE using 0.18μm CMOS technology parameters. The simulation results shows that the proposed circuits are faster and have less transistors in comparison to conventional MCML circuits. Monte Carlo simulations has also been conducted for both the logic styles to study the effect of process variations and the results shows that the proposed circuits are more prone to variations than the conventional one.</description><subject>Adders</subject><subject>Capacitance</subject><subject>CMOS integrated circuits</subject><subject>high speed</subject><subject>Logic gates</subject><subject>MOS current mode logic</subject><subject>Noise</subject><subject>RCA</subject><subject>Transistors</subject><subject>Wireless communication</subject><issn>2325-940X</issn><isbn>9781457711107</isbn><isbn>1457711109</isbn><isbn>9781457711084</isbn><isbn>1457711087</isbn><isbn>1457711095</isbn><isbn>9781457711091</isbn><fulltext>true</fulltext><rsrctype>conference_proceeding</rsrctype><creationdate>2011</creationdate><recordtype>conference_proceeding</recordtype><sourceid>6IE</sourceid><recordid>eNpNkMlOwzAYhI0AiarkCXrxCyR4je1jFbZKVcsBJG6V7fwBQ5bKTqn69kSiB-Yymk-jOQxCC0oKSom5W23uq-2mYITSoqTcSMIvUGaUpkIqNVW0uPyfKVFXaMY4k7kR5P0GZSl9kUllaRg1M_SyxD0ccej2cfiBGvtDjNCPuBtqwO3wETxO46kFfAzjJ24Aamf9N26GOJEILaSE_dB1hz54O4ahv0XXjW0TZGefo7fHh9fqOV9vn1bVcp0HquSYu1IS6xyX1loCwGpdesMbrxQTWlujmJReK-CUSeGoqhtBjLOCK-El95bP0eJvNwDAbh9DZ-Npd_6E_wJVZ1PF</recordid><startdate>201112</startdate><enddate>201112</enddate><creator>Sridhar, R.</creator><creator>Gupta, K.</creator><creator>Pandey, N.</creator><creator>Gupta, M.</creator><general>IEEE</general><scope>6IE</scope><scope>6IL</scope><scope>CBEJK</scope><scope>RIE</scope><scope>RIL</scope></search><sort><creationdate>201112</creationdate><title>A new improved current mode logic style with feedback for wireless communication</title><author>Sridhar, R. ; Gupta, K. ; Pandey, N. ; Gupta, M.</author></sort><facets><frbrtype>5</frbrtype><frbrgroupid>cdi_FETCH-LOGICAL-i175t-b650abb35aaa0ee2d86c93fc772488a97255c87e31254b17df409ba4374c53ca3</frbrgroupid><rsrctype>conference_proceedings</rsrctype><prefilter>conference_proceedings</prefilter><language>eng</language><creationdate>2011</creationdate><topic>Adders</topic><topic>Capacitance</topic><topic>CMOS integrated circuits</topic><topic>high speed</topic><topic>Logic gates</topic><topic>MOS current mode logic</topic><topic>Noise</topic><topic>RCA</topic><topic>Transistors</topic><topic>Wireless communication</topic><toplevel>online_resources</toplevel><creatorcontrib>Sridhar, R.</creatorcontrib><creatorcontrib>Gupta, K.</creatorcontrib><creatorcontrib>Pandey, N.</creatorcontrib><creatorcontrib>Gupta, M.</creatorcontrib><collection>IEEE Electronic Library (IEL) Conference Proceedings</collection><collection>IEEE Proceedings Order Plan All Online (POP All Online) 1998-present by volume</collection><collection>IEEE Xplore All Conference Proceedings</collection><collection>IEEE Electronic Library (IEL)</collection><collection>IEEE Proceedings Order Plans (POP All) 1998-Present</collection></facets><delivery><delcategory>Remote Search Resource</delcategory><fulltext>fulltext_linktorsrc</fulltext></delivery><addata><au>Sridhar, R.</au><au>Gupta, K.</au><au>Pandey, N.</au><au>Gupta, M.</au><format>book</format><genre>proceeding</genre><ristype>CONF</ristype><atitle>A new improved current mode logic style with feedback for wireless communication</atitle><btitle>2011 Annual IEEE India Conference</btitle><stitle>INDCON</stitle><date>2011-12</date><risdate>2011</risdate><spage>1</spage><epage>4</epage><pages>1-4</pages><issn>2325-940X</issn><isbn>9781457711107</isbn><isbn>1457711109</isbn><eisbn>9781457711084</eisbn><eisbn>1457711087</eisbn><eisbn>1457711095</eisbn><eisbn>9781457711091</eisbn><abstract>In this paper, a new logic style named as MOS current mode logic with feedback (MCML-FB) is proposed as an alternative to conventional MOS current mode logic (MCML) for implementing digital circuits in wireless communication systems. The proposed circuit style combines the advantages of conventional MCML and positive feedback to improve the performance of wireless systems. The use of feedback enhances the switching speed of the circuit without increasing its power consumption and also reduces the transistors count. Different MCML-FB based circuits such as XOR, carry and 4-bit ripple carry adder are proposed and simulated in PSPICE using 0.18μm CMOS technology parameters. The simulation results shows that the proposed circuits are faster and have less transistors in comparison to conventional MCML circuits. Monte Carlo simulations has also been conducted for both the logic styles to study the effect of process variations and the results shows that the proposed circuits are more prone to variations than the conventional one.</abstract><pub>IEEE</pub><doi>10.1109/INDCON.2011.6139503</doi><tpages>4</tpages></addata></record> |
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subjects | Adders Capacitance CMOS integrated circuits high speed Logic gates MOS current mode logic Noise RCA Transistors Wireless communication |
title | A new improved current mode logic style with feedback for wireless communication |
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