An On-Chip Network Fabric Supporting Coarse-Grained Processor Array

• Published in: IEEE transactions on very large scale integration (VLSI) systems 2013-01, Vol.21 (1), p.178-182
• Main Authors: PHAM, Phi-Hung, MAU, Phuong, KIM, Jungmoon, KIM, Chulwoo
• Format: Article
• Language: English
• Subjects: Applied sciences; Arrays; Chips; Coarse grained array (CGA); Consumption; Design. Technologies. Operation analysis. Testing; Dynamical systems; Dynamics; Electronics; Embedded systems; Exact sciences and technology; Fabrics; Integrated circuit interconnections; Integrated circuits; Integrated circuits by function (including memories and processors); Network topology; network-on-chip (NoC); on-chip communication network; Probes; Processor arrays; Real time systems; reconfigurable computing; Run time (computers); Semiconductor electronics. Microelectronics. Optoelectronics. Solid state devices; Studies; System-on-a-chip; Topology; Very large scale integration
• ISSN: 1063-8210; 1557-9999
• DOI: 10.1109/TVLSI.2011.2181546

Coarse grained arrays (CGAs) with run-time reconfigurability play an important role in accelerating reconfigurable computing applications. It is challenging to design on-chip communication networks (OCNs) for such CGAs with dynamic run-time reconfigurability whilst satisfying the tight budgets of power and area for an embedded system. This paper presents a silicon-proven design of a 64-PE circuit-switched OCN fabric with a dynamic path-setup scheme capable of supporting an embedded coarse-grained processor array. A proof-of-concept test chip fabricated in a 0.13 μm CMOS process occupies a silicon area of 23 mm 2 and consumes a peak power of 200 mW @ 128 MHz and 1.2 Vcc, at room temperature. The OCN overhead consumes 9.4% of the area and 18% of the power of the total chip. Experimental results and analysis show that the proposed OCN fabric with its dynamic path-setup is suitable for use in an embedded CGA supporting fast run-time reconfigurability.