A software/hardware co-debug platform for multi-core systems

In this paper we present a software/hardware co-debug platform to deal with the various debug problems in multiple-core SOC systems with multiple-clock domains. This platform allows designers to debug embedded processors, buses, IP cores, as well as the application programs being developed. It can b...

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Bibliographic Details
Main Authors: Kuen-Jong Lee, Su, A., Long-Feng Chen, Jia-Wei Jhou, Kuo, J., Liu, M.
Format: Conference Proceeding
Language:English
Subjects:
Clocks
Hardware
Software
Online Access:Request full text
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Description
Summary:In this paper we present a software/hardware co-debug platform to deal with the various debug problems in multiple-core SOC systems with multiple-clock domains. This platform allows designers to debug embedded processors, buses, IP cores, as well as the application programs being developed. It can be used at various design and manufacturing stages including component development, hardware/software co-design, system prototyping, and post-silicon debugging. Three major mechanisms are integrated into this platform, namely a software debug mechanism for multi-core programming, an on-chip hardware debug mechanism for various hardware IPs, and a two-way cross trigger mechanism to synchronize the debug processes of software and hardware. Experimental results on a FPGA prototyping board demonstrate the effectiveness and efficiency of this platform in identifying the root causes of failures for multiple-core SOC systems with multiple-clock domains.
ISSN:2162-7541
2162-755X
DOI:10.1109/ASICON.2011.6157171