A 14-bit 2-GS/s DAC with SFDR>70dB up to 1-GHz in 65-nm CMOS

A 14-bit 2-GS/s 5-5-4 segmented current-steering digital-to-analog converter is presented in this paper. To improve the high frequency performance, a "fast switching" technique which adds additional biasing to the current-switch is adopted. Also data dependent clock loading effect is minim...

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Bibliographic Details
Main Authors: Ran Li, Qi Zhao, Ting Yi, Zhiliang Hong
Format: Conference Proceeding
Language:English
Subjects:
Capacitance
Frequency synchronization
Radio access networks
Switches
Online Access:Request full text
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Summary:A 14-bit 2-GS/s 5-5-4 segmented current-steering digital-to-analog converter is presented in this paper. To improve the high frequency performance, a "fast switching" technique which adds additional biasing to the current-switch is adopted. Also data dependent clock loading effect is minimized with better switch control and double latch method. Post-layout simulation shows that this DAC maintains 70-dB SFDR over Nyquist frequency band up to 2-GS/s and dissipates a power of 82 mW while driving a 50 Ω load with an output swing of 2.5V pp . The chip is designed in 65nm CMOS technology and has an active area of 0.9 mm 2 .
ISSN:2162-7541
2162-755X
DOI:10.1109/ASICON.2011.6157231