Improved extrinsic information scheduling for non-binary cycle codes

Low-density parity-check codes with variable node degree two over high order Galois fields are called non-binary cycle codes. In this paper, several improved extrinsic information scheduling strategies with reduced iteration times are proposed for non-binary cycle codes. Exploiting the property of u...

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Bibliographic Details
Main Authors: Weigang Chen, Li Yu, Jinsheng Yang
Format: Conference Proceeding
Language:English
Subjects:
Complexity theory
Decoding
Hardware
Iterative decoding
Processor scheduling
Throughput
Online Access:Request full text
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Summary:Low-density parity-check codes with variable node degree two over high order Galois fields are called non-binary cycle codes. In this paper, several improved extrinsic information scheduling strategies with reduced iteration times are proposed for non-binary cycle codes. Exploiting the property of underlying sparse graphs for cycle codes, iteration times and hardware complexity including computation units and inner memories can obtain a proper trade-off using the proposed fully serial or turbo scheduling in each iteration. In this way, significant error correction performance can be obtained with less hardware resources and iterations.
DOI:10.1109/ICCT.2011.6157861