Design, integration and implementation of the DySER hardware accelerator into OpenSPARC

• Main Authors: Benson, J., Cofell, R., Frericks, C., Chen-Han Ho, Govindaraju, V., Nowatzki, T., Sankaralingam, K.
• Format: Conference Proceeding
• Language: English
• Subjects: Debugging; Field programmable gate arrays; Instruction sets; Pipelines; Prototypes; Registers
• ISSN: 1530-0897; 2378-203X
• DOI: 10.1109/HPCA.2012.6168949

Accelerators and specialization in various forms are emerging as a way to increase processor performance. Examples include Navigo, Conservation-Cores, BERET, and DySER. While each of these employ different primitives and principles to achieve specialization, they share some common concerns with regards to implementation. Two of these concerns are: how to integrate them with a commercial processor and how to develop their compiler toolchain. This paper undertakes an implementation study of one design point: integration of DySER into OpenSPARC, a design we call OpenSPlySER. We report on our implementation exercise and quantitative results, and conclude with a set of our lessons learned. We demonstrate that DySER delivers on its goal of providing a non-intrusive accelerator design. OpenSPlySERruns on an Virtex-5 FPGA, boots unmodified Linux, and runs most of the SPECINT benchmarks with our compiler. Due to physical design constraints, speedups on full benchmarks are modest for the FPGA prototype. On targeted microbenchmarks, OpenSPlySER delivers up to a 31-fold speedup over the baseline OpenSPARC. We conclude with some lessons learned from this somewhat unique exercise of significantly modifying a commercial processor. To the best of our knowledge, this work is one of the most ambitious extensions of OpenSPARC.