A 1.2V 38nm 2.4Gb/s/pin 2Gb DDR4 SDRAM with bank group and ×4 half-page architecture

DDR4 SDRAM is expected to realize low power consumption and high bandwidth using a 1.2V nominal supply voltage and to be a cost-effective solution for various applications. In this paper, bank group architecture, internal reference voltage level (IVREF) and pre-emphasis to overcome conventional oper...

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Main Authors: Kibong Koo, Sunghwa Ok, Yonggu Kang, Seungbong Kim, Choungki Song, Hyeyoung Lee, Hyungsoo Kim, Yongmi Kim, Jeonghun Lee, Seunghan Oak, Lee, Yosep, Jungyu Lee, Joongho Lee, Hyungyu Lee, Jaemin Jang, Jongho Jung, Byeongchan Choi, Yongju Kim, Youngdo Hur, Yunsaing Kim, Byongtae Chung, Yongtak Kim
Format: Conference Proceeding
Language:English
Subjects:
Current measurement
Delta modulation
Parity check codes
SDRAM
Semiconductor device measurement
Timing
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Summary:DDR4 SDRAM is expected to realize low power consumption and high bandwidth using a 1.2V nominal supply voltage and to be a cost-effective solution for various applications. In this paper, bank group architecture, internal reference voltage level (IVREF) and pre-emphasis to overcome conventional operating frequency range are presented. CS_n to command/address latency (CAL), data bus inversion (DBI) and ×4 half-page architecture are introduced to reduce current consumption. Cyclic redundancy check (CRC) and command and address (CA) parity are adopted to check transmission errors in high bandwidth. Also, read CRC with DBI is calculated in parallel to mitigate calculation time and area penalty. Consequently, our 2Gb DDR4 SDRAM achieves 2.4Gb/s data rate at 1.0V supply voltage.
ISSN:0193-6530
2376-8606
DOI:10.1109/ISSCC.2012.6176869