A 72dB-DR ΔΣ CT modulator using digitally estimated auxiliary DAC linearization achieving 88fJ/conv in a 25MHz BW

The ongoing trend for wide-band, power-efficient continuous-time ΔΣ modulators has led to various implementations, which commonly share the usage of multi-bit quantization, low oversampling ratio and 3 rd or 4 th -order loop-filters [1,2]. In order to improve power efficiency, circuit and architectu...

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Bibliographic Details
Main Authors: Witte, P., Kauffman, J. G., Becker, J., Manoli, Y., Ortmanns, M.
Format: Conference Proceeding
Language:eng ; jpn
Subjects:
Distortion measurement
Linearity
Modulation
Robustness
Signal to noise ratio
Table lookup
Temperature measurement
Online Access:Request full text
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Summary:The ongoing trend for wide-band, power-efficient continuous-time ΔΣ modulators has led to various implementations, which commonly share the usage of multi-bit quantization, low oversampling ratio and 3 rd or 4 th -order loop-filters [1,2]. In order to improve power efficiency, circuit and architectural innovations [1], as well as digital implementation [3] or digital correction of analog circuit parts have been used. To date, the best power vs. performance ratio for ΔΣ modulators with above 10MHz bandwidth is held by [1] with an FoM of 120fJ/conv.
ISSN:0193-6530
2376-8606
DOI:10.1109/ISSCC.2012.6176956