Congestion driven placement for Mesh-based FPGA architecture with local interconnect

In this paper we present an adaptation of a congestion driven placement technique to a Mesh based FPGA architecture containing a local interconnect connections. This techniques aims at spreading out congestion by considering white spaces and avoiding signals bounding boxes overlap. As shown in the e...

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Main Authors: Marrakchi, Z., Turki, M., Rebourg, J., Abid, M., Mehrez, H.
Format: Conference Proceeding
Language:English
Subjects:
Computer architecture
Cost function
Delay
Field programmable gate arrays
Integrated circuit interconnections
Routing
Wires
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creator Marrakchi, Z.
Turki, M.
Rebourg, J.
Abid, M.
Mehrez, H.
description In this paper we present an adaptation of a congestion driven placement technique to a Mesh based FPGA architecture containing a local interconnect connections. This techniques aims at spreading out congestion by considering white spaces and avoiding signals bounding boxes overlap. As shown in the experimentation section this technique reduces required routing channel width efficiently and consequently the device total area by 10% in average. In terms of circuit performance, we notice that congestion alleviation allows timing-driven router to reduce critical path delays despite wirelength increasing. This is due essentially to timing closure improvement.
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fullrecord <record><control><sourceid>ieee_CHZPO</sourceid><recordid>TN_cdi_ieee_primary_6177368</recordid><sourceformat>XML</sourceformat><sourcesystem>PC</sourcesystem><ieee_id>6177368</ieee_id><sourcerecordid>6177368</sourcerecordid><originalsourceid>FETCH-LOGICAL-i90t-d0d8f3c51dc0dcb5f36ae1ab846633e0f573d2ea1152884c7058e1e019dcb0753</originalsourceid><addsrcrecordid>eNo1kE9LAzEUxCMqWGvvgpd8ga3vbZp_x7JYLbToofeSJm9tZJst2aj47S1Y5zIMv2EOw9g9whQR7OOyWU9rQJwq1Fooc8FucSa1rmuw-pJNrDb_WYsrNqpR2gqVghs2GYYPOEmDkFaM2Kbp0zsNJfaJhxy_KPFj5zwdKBXe9pmvadhXOzdQ4Iu35zl32e9jIV8-M_HvWPa8673reEyFsu9TOqE7dt26bqDJ2cdss3jaNC_V6vV52cxXVbRQqgDBtMJLDB6C38lWKEfodmamlBAErdQi1OQQZW3MzGuQhpAA7akNWooxe_ibjUS0PeZ4cPlne_5E_AKV4lNI</addsrcrecordid><sourcetype>Publisher</sourcetype><iscdi>true</iscdi><recordtype>conference_proceeding</recordtype></control><display><type>conference_proceeding</type><title>Congestion driven placement for Mesh-based FPGA architecture with local interconnect</title><source>IEEE Xplore All Conference Series</source><creator>Marrakchi, Z. ; Turki, M. ; Rebourg, J. ; Abid, M. ; Mehrez, H.</creator><creatorcontrib>Marrakchi, Z. ; Turki, M. ; Rebourg, J. ; Abid, M. ; Mehrez, H.</creatorcontrib><description>In this paper we present an adaptation of a congestion driven placement technique to a Mesh based FPGA architecture containing a local interconnect connections. This techniques aims at spreading out congestion by considering white spaces and avoiding signals bounding boxes overlap. As shown in the experimentation section this technique reduces required routing channel width efficiently and consequently the device total area by 10% in average. In terms of circuit performance, we notice that congestion alleviation allows timing-driven router to reduce critical path delays despite wirelength increasing. This is due essentially to timing closure improvement.</description><identifier>ISSN: 2159-1660</identifier><identifier>ISBN: 9781457722073</identifier><identifier>ISBN: 1457722070</identifier><identifier>EISBN: 1457722097</identifier><identifier>EISBN: 9781457722080</identifier><identifier>EISBN: 1457722089</identifier><identifier>EISBN: 9781457722097</identifier><identifier>DOI: 10.1109/ICM.2011.6177368</identifier><language>eng</language><publisher>IEEE</publisher><subject>Computer architecture ; Cost function ; Delay ; Field programmable gate arrays ; Integrated circuit interconnections ; Routing ; Wires</subject><ispartof>ICM 2011 Proceeding, 2011, p.1-5</ispartof><woscitedreferencessubscribed>false</woscitedreferencessubscribed></display><links><openurl>$$Topenurl_article</openurl><openurlfulltext>$$Topenurlfull_article</openurlfulltext><thumbnail>$$Tsyndetics_thumb_exl</thumbnail><linktohtml>$$Uhttps://ieeexplore.ieee.org/document/6177368$$EHTML$$P50$$Gieee$$H</linktohtml><link.rule.ids>309,310,776,780,785,786,2051,27904,54533,54898,54910</link.rule.ids><linktorsrc>$$Uhttps://ieeexplore.ieee.org/document/6177368$$EView_record_in_IEEE$$FView_record_in_$$GIEEE</linktorsrc></links><search><creatorcontrib>Marrakchi, Z.</creatorcontrib><creatorcontrib>Turki, M.</creatorcontrib><creatorcontrib>Rebourg, J.</creatorcontrib><creatorcontrib>Abid, M.</creatorcontrib><creatorcontrib>Mehrez, H.</creatorcontrib><title>Congestion driven placement for Mesh-based FPGA architecture with local interconnect</title><title>ICM 2011 Proceeding</title><addtitle>ICM</addtitle><description>In this paper we present an adaptation of a congestion driven placement technique to a Mesh based FPGA architecture containing a local interconnect connections. This techniques aims at spreading out congestion by considering white spaces and avoiding signals bounding boxes overlap. As shown in the experimentation section this technique reduces required routing channel width efficiently and consequently the device total area by 10% in average. In terms of circuit performance, we notice that congestion alleviation allows timing-driven router to reduce critical path delays despite wirelength increasing. This is due essentially to timing closure improvement.</description><subject>Computer architecture</subject><subject>Cost function</subject><subject>Delay</subject><subject>Field programmable gate arrays</subject><subject>Integrated circuit interconnections</subject><subject>Routing</subject><subject>Wires</subject><issn>2159-1660</issn><isbn>9781457722073</isbn><isbn>1457722070</isbn><isbn>1457722097</isbn><isbn>9781457722080</isbn><isbn>1457722089</isbn><isbn>9781457722097</isbn><fulltext>true</fulltext><rsrctype>conference_proceeding</rsrctype><creationdate>2011</creationdate><recordtype>conference_proceeding</recordtype><sourceid>6IE</sourceid><recordid>eNo1kE9LAzEUxCMqWGvvgpd8ga3vbZp_x7JYLbToofeSJm9tZJst2aj47S1Y5zIMv2EOw9g9whQR7OOyWU9rQJwq1Fooc8FucSa1rmuw-pJNrDb_WYsrNqpR2gqVghs2GYYPOEmDkFaM2Kbp0zsNJfaJhxy_KPFj5zwdKBXe9pmvadhXOzdQ4Iu35zl32e9jIV8-M_HvWPa8673reEyFsu9TOqE7dt26bqDJ2cdss3jaNC_V6vV52cxXVbRQqgDBtMJLDB6C38lWKEfodmamlBAErdQi1OQQZW3MzGuQhpAA7akNWooxe_ibjUS0PeZ4cPlne_5E_AKV4lNI</recordid><startdate>201112</startdate><enddate>201112</enddate><creator>Marrakchi, Z.</creator><creator>Turki, M.</creator><creator>Rebourg, J.</creator><creator>Abid, M.</creator><creator>Mehrez, H.</creator><general>IEEE</general><scope>6IE</scope><scope>6IL</scope><scope>CBEJK</scope><scope>RIE</scope><scope>RIL</scope></search><sort><creationdate>201112</creationdate><title>Congestion driven placement for Mesh-based FPGA architecture with local interconnect</title><author>Marrakchi, Z. ; Turki, M. ; Rebourg, J. ; Abid, M. ; Mehrez, H.</author></sort><facets><frbrtype>5</frbrtype><frbrgroupid>cdi_FETCH-LOGICAL-i90t-d0d8f3c51dc0dcb5f36ae1ab846633e0f573d2ea1152884c7058e1e019dcb0753</frbrgroupid><rsrctype>conference_proceedings</rsrctype><prefilter>conference_proceedings</prefilter><language>eng</language><creationdate>2011</creationdate><topic>Computer architecture</topic><topic>Cost function</topic><topic>Delay</topic><topic>Field programmable gate arrays</topic><topic>Integrated circuit interconnections</topic><topic>Routing</topic><topic>Wires</topic><toplevel>online_resources</toplevel><creatorcontrib>Marrakchi, Z.</creatorcontrib><creatorcontrib>Turki, M.</creatorcontrib><creatorcontrib>Rebourg, J.</creatorcontrib><creatorcontrib>Abid, M.</creatorcontrib><creatorcontrib>Mehrez, H.</creatorcontrib><collection>IEEE Electronic Library (IEL) Conference Proceedings</collection><collection>IEEE Proceedings Order Plan All Online (POP All Online) 1998-present by volume</collection><collection>IEEE Xplore All Conference Proceedings</collection><collection>IEEE Xplore</collection><collection>IEEE Proceedings Order Plans (POP All) 1998-Present</collection></facets><delivery><delcategory>Remote Search Resource</delcategory><fulltext>fulltext_linktorsrc</fulltext></delivery><addata><au>Marrakchi, Z.</au><au>Turki, M.</au><au>Rebourg, J.</au><au>Abid, M.</au><au>Mehrez, H.</au><format>book</format><genre>proceeding</genre><ristype>CONF</ristype><atitle>Congestion driven placement for Mesh-based FPGA architecture with local interconnect</atitle><btitle>ICM 2011 Proceeding</btitle><stitle>ICM</stitle><date>2011-12</date><risdate>2011</risdate><spage>1</spage><epage>5</epage><pages>1-5</pages><issn>2159-1660</issn><isbn>9781457722073</isbn><isbn>1457722070</isbn><eisbn>1457722097</eisbn><eisbn>9781457722080</eisbn><eisbn>1457722089</eisbn><eisbn>9781457722097</eisbn><abstract>In this paper we present an adaptation of a congestion driven placement technique to a Mesh based FPGA architecture containing a local interconnect connections. This techniques aims at spreading out congestion by considering white spaces and avoiding signals bounding boxes overlap. As shown in the experimentation section this technique reduces required routing channel width efficiently and consequently the device total area by 10% in average. In terms of circuit performance, we notice that congestion alleviation allows timing-driven router to reduce critical path delays despite wirelength increasing. This is due essentially to timing closure improvement.</abstract><pub>IEEE</pub><doi>10.1109/ICM.2011.6177368</doi><tpages>5</tpages></addata></record>
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subjects Computer architecture
Cost function
Delay
Field programmable gate arrays
Integrated circuit interconnections
Routing
Wires
title Congestion driven placement for Mesh-based FPGA architecture with local interconnect
url http://sfxeu10.hosted.exlibrisgroup.com/loughborough?ctx_ver=Z39.88-2004&ctx_enc=info:ofi/enc:UTF-8&ctx_tim=2025-01-23T13%3A35%3A50IST&url_ver=Z39.88-2004&url_ctx_fmt=infofi/fmt:kev:mtx:ctx&rfr_id=info:sid/primo.exlibrisgroup.com:primo3-Article-ieee_CHZPO&rft_val_fmt=info:ofi/fmt:kev:mtx:book&rft.genre=proceeding&rft.atitle=Congestion%20driven%20placement%20for%20Mesh-based%20FPGA%20architecture%20with%20local%20interconnect&rft.btitle=ICM%202011%20Proceeding&rft.au=Marrakchi,%20Z.&rft.date=2011-12&rft.spage=1&rft.epage=5&rft.pages=1-5&rft.issn=2159-1660&rft.isbn=9781457722073&rft.isbn_list=1457722070&rft_id=info:doi/10.1109/ICM.2011.6177368&rft.eisbn=1457722097&rft.eisbn_list=9781457722080&rft.eisbn_list=1457722089&rft.eisbn_list=9781457722097&rft_dat=%3Cieee_CHZPO%3E6177368%3C/ieee_CHZPO%3E%3Cgrp_id%3Ecdi_FETCH-LOGICAL-i90t-d0d8f3c51dc0dcb5f36ae1ab846633e0f573d2ea1152884c7058e1e019dcb0753%3C/grp_id%3E%3Coa%3E%3C/oa%3E%3Curl%3E%3C/url%3E&rft_id=info:oai/&rft_id=info:pmid/&rft_ieee_id=6177368&rfr_iscdi=true