Design of a 32nm 7T SRAM Cell based on CNTFET for low power operation

• Main Authors: Prasad, S. Rajendra, Madhavi, B. K., Kishore, K. Lal
• Format: Conference Proceeding
• Language: English
• Subjects: Benchmark testing; CNTFETs; Random access memory
• DOI: 10.1109/ICDCSyst.2012.6188756

The SRAM which functions as the cache for system-on-chip is vital in the electronic industry. Carbon Nanotube FETs (CNTFETs) are considered to be the possible "beyond CMOS" device due to its 1-D transport properties that include low carrier scattering and ballistic transport. Therefore Design of SRAM Cell based on CNTFET is important for Low-power cache memory. In cells, the bit-lines are the most power consuming components because of larger power dissipation in driving long bit-line with large capacitance. The cache write consumes considerable large power due to full voltage swing on the bit-line. This Paper proposes a novel 7T SRAM cell based on CNTFET that only depends on one of bit lines for Write operation and reduce the write-power consumption. The read cycle also improved because of careful transistor sizing. HSPICE simulations of this circuit using Stanford CNFET model shows that 37.2% write power saving, read cycle improvement of 38.6%.