Memory efficient FPGA implementation of motion and disparity estimation for the multiview video coding

• Main Authors: Sampaio, F., Zatt, B., Bampi, S., Agostini, L.
• Format: Conference Proceeding
• Language: English
• Subjects: Bandwidth; Encoding; Field programmable gate arrays; FPGA implementation; High definition video; memory aware; Memory management; multiview video coding; Throughput; VLSI design
• DOI: 10.1109/SPL.2012.6211799

This paper presents a high throughput and low off-chip memory bandwidth Motion and Disparity Estimation architecture targeting the Multiview Video Coding requirements. The ME and DE modules are the critical paths in the multiview encoding process, corresponding to up to 80% of the encoding time. Besides, these two modules are responsible for more than 70% of the off-chip memory accesses. The goal of this work is to design a hardware architecture that deals with these two constraints. The design space exploration points the best balance between area and throughput. Besides, the Memory Hierarchy allows a reduction of 87% for memory accesses when compared to a solution without memory management. The synthesis results for the FPGA implementation show that the ME/DE architecture is able to process up to 5-view HD 1080p multiview videos in real time in a typical prediction structure with 2 reference frames (temporal and disparity neighbors). When compared to related works, this work presents the best efficiency in terms of off-chip memory access and maximum throughput at this data input.