Determination of optimum on-chip bypass capacitor in CMOS VLSI systems to reduce switching noise

An analytical model for switching noise with an on-chip bypass capacitor is presented. To incorporate various design parameters into the model, a differential equation is formulated and solved by Laplace transforms. Based on the model, optimum on-chip capacitor size is determined and compared with H...

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Bibliographic Details
Main Authors: Kanigicheria, B., Sung-Hun Oh, Allee, D.
Format: Conference Proceeding
Language:English
Subjects:
Capacitors
Circuit noise
Differential equations
Inductors
Noise reduction
Packaging
Semiconductor device modeling
System-on-a-chip
Very large scale integration
Working environment noise
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Description
Summary:An analytical model for switching noise with an on-chip bypass capacitor is presented. To incorporate various design parameters into the model, a differential equation is formulated and solved by Laplace transforms. Based on the model, optimum on-chip capacitor size is determined and compared with HSPICE simulation results. In the simulation, a realistic 0.6 /spl mu/m BSIM device model at best process conditions is used and good correlation is demonstrated.
DOI:10.1109/ISCAS.1997.621473