Trade-off analysis of fine-grained power gating methods for functional units in a CPU

High-speed power gating (PG) techniques are useful for reducing leakage power of functional units in a CPU core. This paper analyzes trade off of functional units in a MIPS R3000 based processor with three fine-grained PG methods: the cell-based, row-based and ring-based. Compared with the cell-base...

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Bibliographic Details
Main Authors: Weihan Wang, Ohta, Y., Ishii, Y., Usami, K., Amano, H.
Format: Conference Proceeding
Language:English
Subjects:
Benchmark testing
Central Processing Unit
Leakage Power and Processor
Power Gating
Runtime
Switches
Switching circuits
Transistors
Online Access:Request full text
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Summary:High-speed power gating (PG) techniques are useful for reducing leakage power of functional units in a CPU core. This paper analyzes trade off of functional units in a MIPS R3000 based processor with three fine-grained PG methods: the cell-based, row-based and ring-based. Compared with the cell-based PG technique, which was used in our previous work - Geyser-1 processor, the row-based and ring-based PG technique achieved much smaller area and less implemental cost with a certain additional delay to wake-up latency. The simulation results with benchmark programs show that all three methods can reduce leakage power by 28~54% at 25C.
DOI:10.1109/COOLChips.2012.6216587