Monitoring-driven HW/SW interrupt overload prevention for embedded real-time systems

In the paper, a concept and an early analysis of an embedded hardware/software architecture designed to prevent the software from both timing disturbances and interrupt overloads is outlined. The architecture is composed of an FPGA (MCU) used to run the hardware (software) part of an embedded applic...

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Bibliographic Details
Main Author: Strnadel, J.
Format: Conference Proceeding
Language:English
Subjects:
Context
embedded
Field programmable gate arrays
interrupt
limiter
Memory management
Monitoring
overload
prevention
Real time systems
real-time
Software
Timing
Online Access:Request full text
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Description
Summary:In the paper, a concept and an early analysis of an embedded hardware/software architecture designed to prevent the software from both timing disturbances and interrupt overloads is outlined. The architecture is composed of an FPGA (MCU) used to run the hardware (software) part of an embedded application. Comparing to previous approaches, novelty of the architecture can be seen in the fact it is able to adapt interrupt service rates to the actual software load being monitored with no intrusion to the software. According to the actual software load it is able to buffer all interrupts and related data while the software is highly loaded and redirect the interrupts to the MCU as soon as the software becomes underloaded.
DOI:10.1109/DDECS.2012.6219037