A new SAT-based ATPG for generating highly compacted test sets

The test set size is a highly important factor in the post-production test of circuits. A high pattern count in the test set leads to long test application time and exorbitant test costs. We propose a new test generation approach which has the ability to reduce the test set size significantly. In co...

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Bibliographic Details
Main Authors: Eggersgluss, S., Krenz-Baath, R., Glowatz, A., Hapke, F., Drechsler, R.
Format: Conference Proceeding
Language:eng ; jpn
Subjects:
Automatic test pattern generation
Circuit faults
Compaction
Heuristic algorithms
Integrated circuit modeling
Logic gates
Robustness
Online Access:Request full text
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Summary:The test set size is a highly important factor in the post-production test of circuits. A high pattern count in the test set leads to long test application time and exorbitant test costs. We propose a new test generation approach which has the ability to reduce the test set size significantly. In contrast to previous SAT-based ATPG techniques which were focused on dealing with hard single faults, the proposed approach employs the robustness of SAT-solvers to primarily push test compaction. Furthermore, a concept is introduced how the novel technique can be flexibly integrated into an existing industrial flow to reduce the pattern count. Experimental results on large industrial circuits show that the approach is able to reduce the pattern count of up to 63% compared to state-of-the-art dynamic compaction techniques.
DOI:10.1109/DDECS.2012.6219063