Low power scan by partitioning and scan hold

Scan testing dynamic power consumption can induce reliability problems in the circuit under test (CUT) during manufacturing testing. In this paper, we propose a scan chain partitioning technique, supported by a scan hold mechanism, for low power dissipation during the shift phase of the scan testing...

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Bibliographic Details
Main Authors: Arvaniti, E., Tsiatouhas, Y.
Format: Conference Proceeding
Language:English
Subjects:
Built-in self-test
Clocks
Computer architecture
design for test (DfT)
low power DfT
Microprocessors
Power demand
scan-based test
Vectors
Online Access:Request full text
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Summary:Scan testing dynamic power consumption can induce reliability problems in the circuit under test (CUT) during manufacturing testing. In this paper, we propose a scan chain partitioning technique, supported by a scan hold mechanism, for low power dissipation during the shift phase of the scan testing procedures. Substantial power reductions can be achieved either in built-in self test (BIST) or non-BIST scan-based testing environments, without test application time increase, fault coverage decrease, scan cell reordering and clock gating.
DOI:10.1109/DDECS.2012.6219070