The Effect of Gate Length on Channel Strain of Recessed Source/Drain Si1-xCx

In this study, we experimentally evaluated the effects of scaling on the channel strain in terms of gate lengths. We used transistor arrays incorporating Si1-xCx as a stressor with systematically varying gate and source/drain lengths, and employed the NBD method to measure the channel strain. We als...

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Bibliographic Details
Main Authors: Dae-Hong Ko, Sun-Wook Kim, Dae-Seop Byeon, Sangmo Koo, Mijin Jung, Chopra, S., Yihwan Kim, Hoo-Jeong Lee
Format: Conference Proceeding
Language:English
Subjects:
Carbon
Logic gates
Semiconductor process modeling
Silicon
Strain
Transistors
Online Access:Request full text
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Summary:In this study, we experimentally evaluated the effects of scaling on the channel strain in terms of gate lengths. We used transistor arrays incorporating Si1-xCx as a stressor with systematically varying gate and source/drain lengths, and employed the NBD method to measure the channel strain. We also carried out simulation to check the validity of the NBD data.
DOI:10.1109/ISTDM.2012.6222509