New high-speed and low-power radix-2r multiplication algorithms

In this paper, a new recursive multibit recoding multiplication algorithm is introduced. It provides a general space-time partitioning of the multiplication problem that not only enables a drastic reduction of the number of partial products (N/r), but also eliminates the need of pre-computing odd mu...

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Bibliographic Details
Main Authors: Oudjida, A. K., Liacha, A., Berrandjia, M. L., Chaillet, N.
Format: Conference Proceeding
Language:English
Subjects:
Algorithm design and analysis
Computers
Delay
Energy consumption
Equations
High-Radix Multiplication
Low-Power Multiplication
Mathematical model
Multibit Recoding Multiplication
Partial Product Generator (PPG)
Partitioning algorithms
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Summary:In this paper, a new recursive multibit recoding multiplication algorithm is introduced. It provides a general space-time partitioning of the multiplication problem that not only enables a drastic reduction of the number of partial products (N/r), but also eliminates the need of pre-computing odd multiples of the multiplicand in higher radix (r≥3) multiplication. Based on a mathematical proof that any higher radix-2 r can be recursively derived from a combination of two or a number of lower radices, a series of generalized radix-2 r multipliers are generated by means of primary radices: 2 1 , 2 2 , 2 5 , and 2 8 . A variety of higher-radix (2 3 -2 32 ) two's complement 64×64 bit serial/parallel multipliers are implemented on Virtex-6 FPGA and characterized in terms of multiply-time, energy consumption per multiply-operation, and area occupation for r value varying from 2 to 64. Compared to a recent published algorithm, savings of 21%, 53%, 105% are respectively obtained in terms of speed, power, and area.
DOI:10.1109/FTFC.2012.6231732