Power integrity design tips to minimize the effects of mounting inductance of decoupling capacitors

The simulation and the analysis of a power distribution network (PDN), termed power integrity (PI), are performed in the frequency domain and primarily involve analyzing the power and ground planes and the decoupling capacitors. The capacitors provide a temporary source of localized energy for insta...

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Bibliographic Details
Main Authors: Fizesan, R., Pitica, D.
Format: Conference Proceeding
Language:English
Subjects:
Capacitors
Frequency domain analysis
Impedance
Inductance
Integrated circuits
Noise
Power systems
Online Access:Request full text
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Summary:The simulation and the analysis of a power distribution network (PDN), termed power integrity (PI), are performed in the frequency domain and primarily involve analyzing the power and ground planes and the decoupling capacitors. The capacitors provide a temporary source of localized energy for instantaneous current demands from a IC, and a low-impedance return path for high frequency noise. Capacitors need to be close to the device to perform the decoupling function. Efficient energy transfer from the capacitor to the integrated circuit requires placement of the capacitor at a fraction of a quarter wavelengths of the IC's power pins. The purpose of this paper is to simulate a four layer PCB, with power/ground planes, to evaluate the effectiveness and the importance of decoupling capacitors placement, using tools and methodologies to determine the important factors like performance, cost and board area.
ISSN:1842-0133
DOI:10.1109/OPTIM.2012.6231953