A compact 32-bit AES design for embedded system

Recently, much research has been conducted for security of data transactions on embedded platforms. Advanced Encryption Standard (AES) is considered as one of a candidate algorithm for data encryption/decryption. One important application of this standard is cryptography on smart cards. In this pape...

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Bibliographic Details
Main Authors: Benhadjyoussef, N., Machhout, M., El hadj youssef, W., Tourki, R.
Format: Conference Proceeding
Language:English
Subjects:
Algorithm design and analysis
Encryption
Field programmable gate arrays
Program processors
Throughput
Online Access:Request full text
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Summary:Recently, much research has been conducted for security of data transactions on embedded platforms. Advanced Encryption Standard (AES) is considered as one of a candidate algorithm for data encryption/decryption. One important application of this standard is cryptography on smart cards. In this paper we describe a 32-bits architecture developed for Rijndael algorithm to accelerate execution on 32-bits platforms with reduced memory. Using the FPGA device xc5vfx70t-2ff1136-6, a very low-cost implementation of 375 occupied Slices is obtained under 303.364 MHz frequency.
DOI:10.1109/DTIS.2012.6232955