Concurrent L- and S-band class-E power amplifier in 65nm CMOS

A 65nm CMOS concurrent dual-band two-stage class-E power amplifier (PA) using high voltage extended-drain devices is presented. To implement sub-optimum class-E load impedance at L-band (1.0-1.3GHz) and S-band (2.8-3.1GHz), a concurrent transmission-line based dual-band output matching network is de...

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Bibliographic Details
Main Authors: Ronghui Zhang, Acar, M., Apostolidou, M., van der Heijden, M. P., Leenaerts, D. M. W.
Format: Conference Proceeding
Language:English
Subjects:
Class-E
CMOS integrated circuits
CMOS power amplifier
Dual band
Impedance
Impedance matching
L-band
Power generation
Switches
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Summary:A 65nm CMOS concurrent dual-band two-stage class-E power amplifier (PA) using high voltage extended-drain devices is presented. To implement sub-optimum class-E load impedance at L-band (1.0-1.3GHz) and S-band (2.8-3.1GHz), a concurrent transmission-line based dual-band output matching network is designed. The measurements show a drain efficiency (η) >; 61% and a power-added efficiency (PAE) >; 50.5% for L-band (1.0-1.3GHz) with a output power P out >; 30.4dBm. For S-band (2.8-3.1GHz) a η >; 42.6% and a PAE >; 30% with a P out >; 28.9dBm are achieved. The output power variations are within 0.8dB and 1.6dB, respectively.
ISSN:1529-2517
2375-0995
DOI:10.1109/RFIC.2012.6242267