Plasma etch and low temperature PECVD processes for via reveal applications

This paper will focus on 300mm etch and CVD technologies for via reveal (VR) processing. Data on silicon etching will show that etch rates >;5μm/min, with uniformity ±2.5% and selectivity to the liner oxide around ~200:1 can be achieved on bonded TSV wafers. A novel end-point detection method wil...

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Bibliographic Details
Main Authors: Thomas, D., Buchanan, K., Griffiths, H., Crook, K., Carruthers, M., Ansell, O., Archard, D.
Format: Conference Proceeding
Language:English
Subjects:
Copper
Plasma temperature
Silicon
Sulfur hexafluoride
Temperature
Through-silicon vias
Online Access:Request full text
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Summary:This paper will focus on 300mm etch and CVD technologies for via reveal (VR) processing. Data on silicon etching will show that etch rates >;5μm/min, with uniformity ±2.5% and selectivity to the liner oxide around ~200:1 can be achieved on bonded TSV wafers. A novel end-point detection method will also be presented allowing control of the reveal height. The ability to tune the uniformity from centre fast to edge fast will also be covered. A range of stable, repeatable, dielectric films will be presented having a deposition temperature ;10 MV/cm and leakage current densities
ISSN:0569-5503
2377-5726
DOI:10.1109/ECTC.2012.6249061