A Dynamically Reconfigurable Pixel Processor System Based on Power/Energy-Performance-Accuracy Optimization

We introduce a dynamically reconfigurable framework for implementing single-pixel operations. The system relies on a multiobjective optimization scheme that generates Pareto-optimal realizations in the power/energy-performance-accuracy (PPA/EPA) spaces. The Pareto-optimal realizations and their PPA/...

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Bibliographic Details
Published in:IEEE transactions on circuits and systems for video technology 2013-03, Vol.23 (3), p.488-502
Main Authors: Llamocca, Daniel, Pattichis, M.
Format: Article
Language:English
Subjects:
Accuracy
Applied sciences
Circuit properties
Clocks
Design. Technologies. Operation analysis. Testing
Digital circuits
Dynamic partial reconfiguration (DPR)
Electric, optical and optoelectronic circuits
Electronic circuits
Electronics
Exact sciences and technology
Field programmable gate arrays
field-programmable gate-array (FPGA)
Frequency control
Hardware
Integrated circuits
Integrated circuits by function (including memories and processors)
look-up table (LUT)-based architectures
Nickel
Semiconductor electronics. Microelectronics. Optoelectronics. Solid state devices
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Summary:We introduce a dynamically reconfigurable framework for implementing single-pixel operations. The system relies on a multiobjective optimization scheme that generates Pareto-optimal realizations in the power/energy-performance-accuracy (PPA/EPA) spaces. The Pareto-optimal realizations and their PPA/EPA values are stored in DDR-SDRAM and can be chosen dynamically to meet time-varying constraints. Results are shown in terms of power, accuracy (peak signal-to-noise ratio) of the resulting image, and performance in frames per second. Dynamic PPA/EPA management is implemented using dynamic partial reconfiguration and dynamic frequency control.
ISSN:1051-8215
1558-2205
DOI:10.1109/TCSVT.2012.2210664