Performance evaluation of an IC fabrication system using Petri nets

• Main Authors: Mu Der Jeng, Shih Wei Chou, Chi Liang Chung
• Format: Conference Proceeding
• Language: English
• Subjects: Concurrent computing; Etching; Fabrication; Integrated circuit modeling; Lithography; Petri nets; Resource management; Routing; System recovery; Transistors
• ISSN: 1062-922X; 2577-1655
• DOI: 10.1109/ICSMC.1997.625761

IC wafer fabrication is a multi-stage process with reentrant flows, including various operations such as photolithography, diffusion, etching, and thin film. A typical wafer undergoes hundreds of process steps using different resources over the period of a few weeks. Such a system reveals many important characteristics such as resource sharing, asynchronous behavior, concurrency, deadlocks, routing flexibility, mutual exclusion, and lot sizes. Petri nets have been successfully applied to modeling such systems, due to the advantage of the mathematical analysis capability for computing both qualitative properties and quantitative data, and the graphical nature for ease of visualizing the system dynamics. In this paper, using the Petri net methodologies, we present the modeling and performance evaluation of the etching area in an IC fabrication system for producing 0.44 /spl mu/m 4MB DRAMs. The simulation technique is adopted for performance analysis. The result shows that except a small number of machines, the error between simulated and actual utilization ratios of a machine is less than 5%. This indicates that the proposed Petri net method is feasible and practical.