PDN impedance analysis of TSV-decoupling capacitor embedded Silicon interposer for 3D-integrated CMOS image sensor system

• Main Authors: Kikuchi, K., Ueda, C., Fujii, F., Akiyama, Y., Watanabe, N., Kitamura, Y., Gomyo, T., Ookubo, T., Koyama, T., Kamada, T., Aoyagi, M., Otsuka, K.
• Format: Conference Proceeding
• Language: English
• Subjects: Analytical models; Capacitors; CMOS image sensor; decoupling capacitor; Impedance; Integrated circuit modeling; Large scale integration; Power distribution network; Silicon; silicon interposer; through silicon via; Through-silicon vias
• DOI: 10.1109/3DIC.2012.6263017

We have proposed to use the electrostatic capacitance of through-silicon-vias (TSV) in the silicon interposer as the decoupling capacitor. Because the electrostatic capacity of the TSV acts as a decoupling capacitor, it is enabled to decrease the power distribution network (PDN) impedance. Therefore, the dependency to the PDN impedance in the effect of the layout and the shape of the TSV capacitor was analyzed. By introducing the 3-D electromagnetic field simulator, precise PDN impedance analysis was carried out. As a result, TSV functions enough as a decoupling capacitor. PDN impedance of the silicon inter-poser with TSV-decoupling capacitor decrease compared with that of the silicon interposer without TSV. Especially, PDN impedance of the silicon interposer with 200-micrometer pitch TSVs shows PDN impedance without the resonance peak from the low-frequency region to the high frequency area.