Performance evaluation of a flow control algorithm for Network-on-Chip

• Main Authors: Bakhouya, M., Chariete, A., Gaber, J., Wack, M., Niar, S., Coatanea, E.
• Format: Conference Proceeding
• Language: English
• Subjects: Adaptation models; Analytical models; Educational institutions; Flow control and congestion; Modeling/simulation and evaluation; Network-on-chip; Routing; Switches; System-on-a-chip
• DOI: 10.1109/HPCSim.2012.6266925

Network-on-chip (NoC) has been proposed for SoC (System-on-Chip) as an alternative to on-chip bus-based interconnects to achieve better performance and lower energy consumption. Several approaches have been proposed to deal with NoCs design and can be classified into two main categories, design-time approaches and run-time approaches. Design-time approaches are generally tailored for an application domain or a specific application by providing a customized NoC. All parameters, such as routing and switching schemes, are defined at design time. Run-time approaches, however, provide techniques that allow a NoC to continuously adapt its structure and its behavior (i.e., at runtime). In this paper, performance evaluation of a flow control algorithm for congestion avoidance in NoCs is presented. This algorithm allows NoC elements to dynamically adjust their inflow by using a feedback control-based mechanism. Analytical and simulation results are reported to show the viability of this mechanism for congestion avoidance in NoCs.