Hybrid processor population for odor processing

• Main Authors: Ayhan, Tuba, Yeniceri, Ramazan, Ergunay, Selman, Yalein, Mustak Erhan
• Format: Conference Proceeding
• Language: English
• Subjects: Equations; Feature extraction; Field programmable gate arrays; Mathematical model; Process control; Registers; Sensors
• ISSN: 0271-4302; 2158-1525
• DOI: 10.1109/ISCAS.2012.6271607

Some computationally complex problems require complex solutions in terms of number of processors and diversity of computation methods. Metabolic systems are naturally capable of solving complex problems; they are mathematically modelled with hundreds of differential equations. In order to understand those metabolisms or simply replicate their functions in engineering problems, we need a large network of processors that is designed to mimic biological systems. Moreover, many processes take place in metabolic networks are results of collaboration of different types of cells that are randomly located. Therefore, bio-inspired topologically random mega-core networks of hybrid processors are needed to solve complex biological problems. Introducing randomness into a hybrid processor network that employs thousands of processors requires special techniques. We are proposing a solution to mega-core architectures with multi-type processors. Our aim in this work is to obtain a very large collaborative network of hybrid processors that has reconfigurable random topology. Our solution provides reconfiguration of a large network with different types of processors so that the network can be adapted to many different problems or can be used to mimic different metabolic functions. In this work, we are trying to solve the speed problem in artificial olfaction systems by a hybrid processor feature extractor that performs spatio-temporal coding inspired from nature. The technique is also efficient in realization; it is based on adding an 'identity' pin that will be used to reconfigure the identical processors. In this work we propose our technique to generate hybrid processor populations on any array platform or networks of single type processors and report the implementation on FPGA.