Coding for jointly optimizing energy and peak current in deep sub-micron VLSI interconnects

In deep sub-micron processes, on-chip interconnect is becoming the delay bottleneck and predominant source of power consumption. Simultaneous switching of large buses pose a great challenge on peak current as well. In this paper, we present a novel bus coding technique, based on transition pattern c...

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Bibliographic Details
Main Authors: Kim, E. P., Hun-Seok Kim, Goel, M.
Format: Conference Proceeding
Language:English
Subjects:
Cost function
Decoding
Delay
Encoding
Joints
Very large scale integration
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Summary:In deep sub-micron processes, on-chip interconnect is becoming the delay bottleneck and predominant source of power consumption. Simultaneous switching of large buses pose a great challenge on peak current as well. In this paper, we present a novel bus coding technique, based on transition pattern codes (TPC), to perform joint optimization. A TPC scheme has been constructed employing a joint cost function on energy and peak current. The encoder and decoder of the code has been synthesized using a commercial 28nm process and the power, delay and area overhead has been evaluated. HSPICE simulations in 28nm show up to 70% reduction in peak current and 15% reduction in energy consumption compared to an uncoded bus.
ISSN:0271-4302
2158-1525
DOI:10.1109/ISCAS.2012.6271974