Hardware-efficient VLSI implementation for 3-parallel linear-phase FIR digital filter of odd length

• Main Authors: Yu-Chi Tsao, Ken Choi
• Format: Conference Proceeding
• Language: English
• Subjects: Adders; Filtering algorithms; Finite impulse response filter; Hardware; Very large scale integration
• ISSN: 0271-4302; 2158-1525
• DOI: 10.1109/ISCAS.2012.6272215

Based on fast FIR algorithms (FFA), this paper proposes new 3-parallel finite-impulse response (FIR) filter structures, which are beneficial to symmetric convolutions of odd length in terms of the hardware cost. The proposed 3-parallel FIR structures exploit the inherent nature of the symmetric coefficients of odd length, according to the length of filter, (N mod 3), reducing half the number of multipliers in subfilter section at the expense of additional adders in preprocessing and postprocessing blocks. The overhead from the additional adders in preprocessing and postprocessing blocks stay fixed, not increasing along with the length of the FIR filter, whereas the number of reduced multipliers increases along with the length of the FIR filter. For example, for a 81-tap filter, the proposed A structure saves 26 multipliers at the expense of 5 adders, whereas for a 591-tap filter, the proposed structure saves 196 multipliers at the expense of 5 adders still. Overall, the proposed 3-parallel FIR structures can lead to significant hardware savings for symmetric coefficients of odd length from the existing FFA parallel FIR filter, especially when the length of the filter is large.