Customized instruction set simulation for soft-core RISC processor

• Main Authors: Salim, A. J., Salim, S. I. M., Samsudin, N. R., Yewguan Soo
• Format: Conference Proceeding
• Language: English
• Subjects: ASIP; Assembly; Computational modeling; Computer architecture; Field programmable gate arrays; instruction set; Process control; Reduced instruction set computing; Registers; RISC
• DOI: 10.1109/ICSGRC.2012.6287132

This paper presents the instruction set simulation process for soft-core Reduced Instruction Set Computer (RISC) processor. The aim of this paper is to provide reliable simulation platform in creating customizable instruction set for Application Specific Instruction Set Processor (ASIP). The targeted RISC processor is based on basic 8-bit PIC16C5X-compatible processor where the architecture is reconfigurable through Hardware Description Language (HDL). Instruction set architecture (ISA) has been modified in term of instruction width and machine instruction. Memory address remapping algorithm is introduced to remap the memory address to correct physical memory address due to memory banking scheme being applied. A total number of 34 instruction sets are simulated and verified its operations. Selected instruction set has been reconfigured from its original operation to demonstrate the ability to modify current instruction set to suit certain specialized application. The simulation is done using a Java-based CPU architecture simulation program and data movements at file register array and memory registers are monitored to verify the correct working operation of each instruction set. The instruction set simulation process is proved capable to be the starting point in creating a reconfigurable RISC processor with customized instruction set, inline with ASIP methodology.