Ultra Low Power Circuit Design Using Tunnel FETs

The proliferation of ubiquitous and mobile computing systems has created a new segment in the design space where energy efficiency is the most critical design parameter. With the end user expecting more functionality from these types of systems, there is a pressing need to evaluate emerging technolo...

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Bibliographic Details
Main Authors: Mukundrajan, R., Cotter, M., Saripalli, V., Irwin, M. J., Datta, S., Narayanan, V.
Format: Conference Proceeding
Language:English
Subjects:
Adders
Circuit synthesis
Energy consumption
Energy-efficiency
FETs
Integrated circuit modeling
Low-Power
Switches
Tunnel FET
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Summary:The proliferation of ubiquitous and mobile computing systems has created a new segment in the design space where energy efficiency is the most critical design parameter. With the end user expecting more functionality from these types of systems, there is a pressing need to evaluate emerging technologies that can overcome the limitations of CMOS. This work evaluates the potential of one such prospective MOSFET replacement device - the Tunnel FET (TFET). Novel circuit designs are presented to overcome unique design challenges posed by TFETs. The impacts of the proposed design techniques are characterized and a sparse prefix tree adder employing the proposed designs is presented. A considerable improvement in delay and significant reduction in energy is observed due to the combined impact of circuit and technology co-exploration.
ISSN:2159-3469
2159-3477
DOI:10.1109/ISVLSI.2012.70