An 8-b 400-MS/s 2-b-Per-Cycle SAR ADC With Resistive DAC

An 8-b 400-MS/s 2-b-per-cycle (2 b/C) successive approximation register (SAR) analog-to-digital converter (ADC) is fabricated in 65-nm CMOS. With the implementation of a low-power and small-area resistive DAC and associated highly integrated circuit implementation, the proposed SAR ADC achieves rapi...

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Bibliographic Details
Published in:IEEE journal of solid-state circuits 2012-11, Vol.47 (11), p.2763-2772
Main Authors: Hegong Wei, Chi-Hang Chan, U-Fat Chio, Sai-Weng Sin, Seng-Pan U, Martins, R. P., Maloberti, F.
Format: Article
Language:English
Subjects:
2-b-per-cycle (2 b/C)
Analog-to-digital converter (ADC)
Applied sciences
Calibration
Capacitance
Circuit properties
Clocks
Decoding
Design. Technologies. Operation analysis. Testing
Electric, optical and optoelectronic circuits
Electronic circuits
Electronics
Exact sciences and technology
Integrated circuits
Interpolation
Registers
resistive DAC
Semiconductor electronics. Microelectronics. Optoelectronics. Solid state devices
Signal convertors
successive approximation register (SAR)
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Summary:An 8-b 400-MS/s 2-b-per-cycle (2 b/C) successive approximation register (SAR) analog-to-digital converter (ADC) is fabricated in 65-nm CMOS. With the implementation of a low-power and small-area resistive DAC and associated highly integrated circuit implementation, the proposed SAR ADC achieves rapid conversion rate, low power, and compact area, leading to SNDR of 44.5 dB and SFDR of 54.0 dB, at 400 MS/s with 1.9-MHz input. The measured FOM is 73 fJ/conversion-step at 400 MS/s from 1.2-V supply and 42 fJ/conversion-step at 250 MS/s from a 1-V supply. The active area with the digital calibration is 0.028 mm 2 .
ISSN:0018-9200
1558-173X
DOI:10.1109/JSSC.2012.2214181