Design and implementation of a new symmetric Built-in Redundancy analyzer

With the advance of VLSI technology and growth of embedded memory density, a corresponding increase in the number of defects has resulted in yield and quality degradation. Built-in Self-Repair (BISR) solves this problem by replacing faulty cells with healthy redundant cells. Built-in Redundancy anal...

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Bibliographic Details
Main Authors: Habiby, P., Asli, R. N.
Format: Conference Proceeding
Language:English
Subjects:
Algorithm design and analysis
built-in redundancy analyzer
built-in self repair
Circuit faults
embedded memory
Maintenance engineering
Memory management
Redundancy
System-on-a-chip
Very large scale integration
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Summary:With the advance of VLSI technology and growth of embedded memory density, a corresponding increase in the number of defects has resulted in yield and quality degradation. Built-in Self-Repair (BISR) solves this problem by replacing faulty cells with healthy redundant cells. Built-in Redundancy analyzer (BIRA) as a key component of BISR performs redundancy analysis and spare allocation. In this paper we used the symmetry feature of binary search tree to reduce the BIRA hardware overhead. Implementation results of the proposed BIRA for a 2×2 redundancy configuration are presented.
ISSN:2325-9361
DOI:10.1109/CADS.2012.6316427