Considerations for the design of an SRAM with SOI technology

A silicon-on-insulator process that has a thin silicon film and source/drain junctions driven to the underlying insulator and that provides significant advantages for fabrication of an SRAM for space applications, is presented. The advantages result primarily from a reduced collection volume for ups...

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Bibliographic Details
Published in:IEEE circuits and devices magazine 1987-11, Vol.3 (6), p.8-10
Main Author: Houston, T. W.
Format: Article
Language:English
Subjects:
Capacitance
Computer architecture
Junctions
Materials
Microprocessors
Silicon on insulator technology
Transistors
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Description
Summary:A silicon-on-insulator process that has a thin silicon film and source/drain junctions driven to the underlying insulator and that provides significant advantages for fabrication of an SRAM for space applications, is presented. The advantages result primarily from a reduced collection volume for upset from an ionizing particle and the possibility of fitting larger devices in a memory-cell area limited by interconnection pitch. The reduced junction capacitance would also give an SRAM fabricated with such a process an advantage for the general high-performance SRAM market.
ISSN:8755-3996
1558-1888
DOI:10.1109/MCD.1987.6323173