A 28.3 mW PA-Closed Loop for Linearity and Efficiency Improvement Integrated in a + 27.1 dBm WCDMA CMOS Power Amplifier

A wideband feedback linearization technique for a power amplifier (PA), PA-closed loop, is presented. In order to achieve wideband operation, it employs a two-path feedback scheme where the input and output phases and amplitudes are detected at RF and compared to directly control and linearize the P...

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Bibliographic Details
Published in:IEEE journal of solid-state circuits 2012-12, Vol.47 (12), p.2964-2973
Main Authors: Kousai, Shouhei, Onizuka, K., Yamaguchi, T., Kuriyama, Y., Nagaoka, M.
Format: Article
Language:English
Subjects:
Amplifiers
Applied sciences
Circuit properties
CMOS power amplifier
Design. Technologies. Operation analysis. Testing
efficiency improvement
Electric, optical and optoelectronic circuits
Electrical engineering. Electrical power engineering
Electronic circuits
Electronic equipment and fabrication. Passive components, printed wiring boards, connectics
Electronics
Exact sciences and technology
feedback
Feedback communications
Gain
Integrated circuits
Linearity
linearization
Logic gates
PA-closed loop
Power electronics, power supplies
Power generation
Radio frequency
Semiconductor electronics. Microelectronics. Optoelectronics. Solid state devices
Wideband
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Summary:A wideband feedback linearization technique for a power amplifier (PA), PA-closed loop, is presented. In order to achieve wideband operation, it employs a two-path feedback scheme where the input and output phases and amplitudes are detected at RF and compared to directly control and linearize the PA. The wideband characteristic of the loop suppressed the adjacent channel leakage ratio (ACLR) for WCDMA standard by 6 dB. The advantage of the feedback is demonstrated by measuring the performance against the load variation. The required back-off is degraded by only 1 dB with a voltage standing wave ratio (VSWR) of 1.5, whereas it is 3 dB without the loop. The loop consumes 28.3 mW and it reduces the quiescent power consumption of the PA by 78 mW. The chip, which integrates the loop and PA, is fabricated in a 0.13 μm CMOS technology and the loop occupies 0.3 mm by 0.7 mm. The PA delivers WCDMA output power of 27.1 dBm with a power added efficiency (PAE) of 28% and ACLR of 40 dBc. This topology makes possible the wideband feedback linearization of a watt-level PA.
ISSN:0018-9200
1558-173X
DOI:10.1109/JSSC.2012.2217833